this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 1 EN71NS128C0 rev. b, issue date: 2011 / 06 / 16 distinctive characteristics mcp features power supply voltage of 1.7v to 1.95v high performance - 70 ns @ random access - 7 ns @ burst access (108mhz) package - 6.2 x 7.7 x 1.0mm 56 ball bga operating temperature - 25 c to +85 c general description the en71ns series is a product line of stacked multi-chip product (mcp) packages and consists of: e29ns128 (burst mode) flash memory die. pseudo sram. for detailed specifications, please refer to the indi vidual datasheets listed in the following table. device document nor flash en29ns128 pseudo sram enpsmc5 product selector guide 128 mb flash memories device-model# EN71NS128C0 psram density 64m psram flash access time 70ns at async. mode 7ns at burst read psram access time 70ns at async. mode 7ns at burst read psram burst mode max frequency 108mhz psram burst mode max frequency 108mhz package 56-ball bga EN71NS128C0 base mcp stacked multi-chip product (mcp) flash memory and ram 128 megabit (8m x 16-bit) cmos 1.8 volt-only simultaneous operation burst mode flash memory and 64 megabit (4m x 16-bit) pseudo static ram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 2 EN71NS128C0 rev. b, issue date: 2011 / 06 / 16 mcp block diagram nor flash + psram diagram note: amax = a22
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 3 EN71NS128C0 rev. b, issue date: 2011 / 06 / 16 connection diagram mcp flash-only addresses shared addresses shared adq pins EN71NS128C0 a22 a21 ? a16 adq15 ? adq0
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 4 EN71NS128C0 rev. b, issue date: 2011 / 06 / 16 pin description symbol description flash psram a22?a16 address inputs adq15?adq0 multiplexed address/data oe# output enable input. asynchronous relative to clk for the burst mode. we# write enable input. vssq/vss ground vccq/vcc device power supply (1.7 v?1.95 v). nc not contact; pin not connected internally rdyf/waitp ready output; indicates the status of the burst read. flash memory rdy (using default ?active high? configuration) v ol = data invalid, v oh = data valid. note: the default polarity for the psram wait signal is opposite the default polarity of the flash rdy signal. psram wait (using default ?active high? configuration) v ol = data valid, v oh = data invalid. to match polarities, change bit 10 of the psram bus configruation register to 0 (active low wait). alternately, change bit 10 of the flash configuration register to 0 (active low rdy) clk clock input. in burst mode, afte r the initial word is output, subsequent active edges of clk increment the internal address counter. should be at v ol or v ih while in asynchronous mode. avd# address valid input. indicates to device that the valid address is present on the address inputs. v il = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of clk. v ih = device ignores address inputs reset# f hardware reset input. v il = device resets and returns to reading array data wp#f hardware write protect input. v il = disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. accf accelerated input. at v hh , accelerates programming; automatically places device in accelerated program mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. (applying high voltage on mcp package is prohibited; otherwise, internal ram may be damaged easily!) ce# p chip enable input for psram. ce# f chip enable input for flash. asynchronous relative to clk for the burst mode. crep control register enable (psram). lb#p lower byte enable. dq7~dq0 (psram) ub#p upper byte enable. dq15~dq8 (psram) rfu reserved for future use
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 5 EN71NS128C0 rev. b, issue date: 2011 / 06 / 16 operating mode (for asynchronous mode) asynchronous mode bcr[15]=1 power clk adv# ce# oe# we# cre ub#/ lb# wait 2 a/dq[15:0] read active x l l h l l low-z data out write active x l x l l l high-z data in standby standby h or l x h x x l x high-z high-z no operation idle x x l x x l x low-z x configuration register write active x l h l h x low-z high-z configuration register read active x l l h h l low-z config. reg.out operating mode (for synchronous burst mode) burst mode bcr[15]=0 power clk adv# ce# oe# we# cre ub#/ lb# wait a/dq[15:0] async read active h or l l l h l l low-z data out async write active h or l l x l l l high-z data in standby standby h or l x h x x l x high-z high-z no operation idle h or l x l x x l x low-z x initial burst read active l l x h l l low-z address initial burst write active l l h l l x low-z address burst continue active h l x x x l low-z data out or data in configuration register write active l l h l h x low high-z configuration register read active l l l h h l low config. reg.out note: x=don?t care. h=logic high. l=logic low. v= valid data
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 6 EN71NS128C0 rev. b, issue date: 2011 / 06 / 16 ordering information en71ns 128 c0 - 7 dc w p packaging content p = rohs compliant temperature range w = wireless (-25 c to +85 c) package dc = 56-ball bga 0.50mm pitch, 6.2m m x 7.7mm package burst read access time 7 = 108 mhz pseudo sram density c0 = 64mb density 128 = 128megabit (8m x 16 bit) base part number en = eon silicon solution inc. 71ns = multi-chip product (mcp) 1.8v simultaneous read/write, burst-mode multiplexed flash and ram
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 7 EN71NS128C0 rev. b, issue date: 2011 / 06 / 16 package mechanical 56-ball ball grid array (bga) 6.2 x 7.7 x 1.0mm package, pitch: 0.5mm, ball: 0.3mm min. nor max a - - - - - - 1.00 a1 0.16 - - - 0.26 a2 d 6.106.206.30 e 7.607.707.80 d1 e1 e b 0.27 - - - 0.37 dimension in mm symbol note : 1. coplanarity: 0.1 mm 0.676 4.5 bsc 6.5 bsc 0.5 bsc
this data sheet may be revised by subsequent versions ?2004 eon silicon solution, inc., www.eonssi.com or modifications due to changes in technical specifications. 8 EN71NS128C0 rev. b, issue date: 2011 / 06 / 16 revisions list revision no description date a initial release 2010/11/23 b change pseudo sram from enpss64 to enpsmc5. 2011/06/16
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